This application claims priority from Korean Patent Application No. 99-24218, filed on Jun. 25, 1999, and Korean Patent Application No. 99-24219, filed on Jun. 25, 1999.
The present invention relates to a capacitor for a semiconductor memory device and a method of manufacturing the same.
With recent progress in semiconductor manufacturing technology, the demand for memory devices has increased dramatically. Generally, a memory device having high capacitance is desirable. Capacitance of the capacitor can be increased by using a dielectric layer having a high dielectric constant or by enlarging the surface area of a lower electrode. Those conventional capacitors are made with a Ta2O5 layer having a dielectric constant higher than that of nitride-oxide(NO), thereby forming the lower electrode of a 3-dimensional structure.
FIG. 1 is a cross-sectional view of a capacitor in a conventional semiconductor memory device. Referring to FIG. 1, a field oxide layer 11 is formed at a predetermined portion of a substrate 10, a gate electrode 13 including a gate insulating layer 12 at a lower portion thereof is formed by a known technique at a predetermined portion of a semiconductor substrate 10. A junction region 14 is formed on semiconductor substrate 10 at each end of gate electrode 13, thereby forming a MOS transistor. A first interlevel insulating layer 16 and a second interlevel insulating layer 18 are formed on semiconductor substrate 10. A storage-node contact hole h is formed in the first and second interlevel insulating layers 16 and 18 so that the junction region 14 is exposed. A cylindrical type lower electrode 20 is formed by a known technology within the storage-node contact hole h to contact the exposed junction region 14. A hemispherical grain (HSG) layer 21 is formed on a surface of lower electrode 20 in order to increase the surface area of lower electrode 20. A Ta2O5 layer 23 is formed on the surface of HSG layer 21. At this time, Ta2O5 layer 23 is formed as follows. First, a surface of HSG layer 21 is cleaned before the Ta2O5 layer 23 is formed, and then the RTN (rapid thermal nitridation) process is performed externally thereby forming a silicon-nitride layer 22 on HSG layer 21. Next, a first Ta2O5 layer is formed at 30 temperature of approximately 400xcx9c450xc2x0 C. with a thickness of 53xcx9c57 xc3x85. Afterward, an annealing process is performed at low temperature, and then a second Ta2O5 layer is formed with the same thickness and by the same process as in the first Ta2O5 layer. Annealing processes at low and at high temperatures are continued in series thereby forming a single Ta2O5 layer 23. An upper electrode 24 is deposited on upper portions of the Ta2O5 layer and the second interlevel insulating layer 18, thereby completing the formation of a capacitor.
However, the conventional capacitor formed according to the above method using Ta2O5 as a dielectric layer has the following problems. First, a difference in the composition rate of Ta and 0 results since Ta2O5 generally has unstable stoichiometry. As a result, substitutional Ta atoms, i.e., vacancy atoms, are generated in the Ta2O5 layer. Since those vacancy atoms are oxygen deprived, leakage current results. The amount of vacancy atoms in the dielectric layer can be controlled depending on the contents and the bond strength of components in the Ta2O5 layer; however, it is difficult to eliminate them completely.
In order to stabilize the unstable stoichiometry of Ta2O5, the Ta2O5 layer is oxidized to remove the substitutional Ta atoms in the Ta2O5 layer. However, when the layer is oxidized, an oxide layer having a low dielectric constant is formed at an interface between the Ta2O5 layer and the lower electrode or between the Ta2O5 layer and the upper electrode since Ta2O5 easily oxidizes with the lower and upper electrodes made of polysilicon or TiN, thereby degrading the homogeneity of the interface.
Further, due to the reaction between an organic substance such as Ta(OC2H5)5 used as a precursor and O2(or N2O) gas as a reaction gas, impurities result, such as carbon atoms C, carbon compounds(CH4, C2H4) and H2O in the Ta2O5 layer. These impurities increase leakage current in the capacitor and degrade the dielectric characteristics of the Ta2O5 layer. Accordingly, a capacitor having a large capacitance is difficult to obtain.
Moreover, the use of the Ta2O5 layer as a dielectric layer generates extra ex situ steps; one before formation of Ta2O5 layer and one after the cleaning step. Also, two thermal processes, at low and high temperatures, preferably are performed after the Ta2O5 layer has been formed. Therefore, forming a dielectric layer with Ta2O5 using a conventional method is cumbersome.
Accordingly, one object of the present invention is to provide a capacitor for a semiconductor device capable of obtaining a great capacitance by providing a dielectric layer having a high dielectric constant and which incurs little leakage current.
Furthermore, the other object of the present invention is to provide a method of manufacturing a capacitor for semiconductor device capable of simplifying its manufacturing process.
In order to accomplish the foregoing objects of the present invention, according to one embodiment, the present invention provides a capacitor for a semiconductor memory device having a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer, wherein the dielectric layer is a TaON layer.
According to another embodiment of the present invention, a method includes the steps of: forming a lower electrode on the semiconductor substrate; depositing a TaON layer as a dielectric layer on the lowerelectrode; and forming an upper electrode on the TaON layer.
Furthermore, according to the present invention, a method includes the steps of: forming a lower electrode on the semiconductor substrate; surface-treating to prevent generation of a natural oxide layer on a surface of the lower electrode; depositing a TaON layer as a dielectric layer on the lower electrode; out-diffusing impurities remaining in the TaON layer and crystallizing the TaON layer; and forming an upper electrode on the TaON layer.
Also, according to the present invention, a method includes the steps of: forming a lower electrode on the semiconductor substrate; surface-treating to prevent generation of a natural oxide layer on a surface of the lower electrode; depositing a TaON layer as a dielectric layer on the lower electrode; out-diffusing impurities remaining in the TaON layer and crystallizing the TaON layer; and forming an upper electrode on the TaON layer, wherein in the step of depositing the TaON layer, the TaON layer is formed by a surface chemical vapor reaction of Ta obtained from a precursor, O2 gas and NH3 gas in at a low pressure chemical vapor deposition (LPCVD) chamber to which O2 gas and NH3 gas are supplied a pressure of 0.1xcx9c10 Torr at a temperature of 300xcx9c600xc2x0 C. respectively.
According to another embodiment of the present invention, a method includes the steps of: forming a lower electrode on the semiconductor substrate; surface-treating to prevent generation of a natural oxide layer on a surface of the lower electrode; depositing a TaON layer as a dielectric layer on the lower electrode; out-diffusing impurities remaining in the TaON layer and crystallizing the TaON layer; and forming an upper electrode on the TaON layer, wherein in the step of depositing the TaON layer, the TaON layer is formed by a surface chemical vapor reaction of Ta obtained from a precursor, O2 gas and NH3 gas in an LPCVD chamber to which O2 gas and NH3 gas are supplied at a pressure of 0.1xcx9c10 Torr at a temperature of 300xcx9c600xc2x0 C. wherein the surface-treatment of the lower electrode is performed in the LPCVD chamber by using plasma in situ in an NH3 gas or N2/H2 gas atmosphere at a temperature of 300xcx9c600xc2x0 C. for 30 secondsxcx9c5 minutes, thereby nitrifying the surface of the lower electrode.